DSPIC30F4011-30I/ML【PDF 21/238 页】IC DSPIC MCU/DSP 48K 44QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1917

17页 18页 19页 20页 [21页]22页 23页 24页 25页

2010 Microchip Technology Inc.

DS70135G-page 117

dsPIC30F4011/4012

17.7

Interrupts

The I2C module generates two interrupt flags, MI2CIF

(I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter-

rupt Flag). The MI2CIF interrupt flag is activated on

completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

17.8

Slope Control

The I2C standard requires slope control on the SDA

and SCL signals for Fast mode (400 kHz). The control

bit, DISSLW, enables the user to disable slew rate con-

trol, if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

17.9

IPMI Support

The control bit, IPMIEN, enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

17.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an Acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R_W = 0.

The general call address is recognized when the Gen-

eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).

Following a Start bit detection, 8 bits are shifted into

I2CRSR and the address is compared with I2CADD,

and is also compared with the general call address

which is fixed in hardware.

If a general call address match occurs, the I2CRSR is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set, and on the falling edge of the ninth bit

(ACK bit), the Master Event Interrupt Flag (MI2CIF) is

set.

When the interrupt is serviced, the source for the interrupt

can be checked by reading the contents of the I2CRCV

to determine if the address was device-specific or a

general call address.

17.11 I2C Master Support

As a master device, six operations are supported.

Assert a Start condition on SDA and SCL.

Assert a Restart condition on SDA and SCL.

Write to the I2CTRN register initiating

transmission of data/address.

Generate a Stop condition on SDA and SCL.

Configure the I2C port to receive data.

Generate an ACK condition at the end of a

received byte of data.

17.12 I2C Master Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this case, the data direction bit (R_W) is logic ‘0’. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted, an ACK bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the data direction bit. In this case, the data

direction bit (R_W) is logic ‘1’. Thus, the first byte

transmitted is a 7-bit slave address, followed by a ‘1’ to

indicate the receive bit. Serial data is received via SDA

while SCL outputs the serial clock. Serial data is

received 8 bits at a time. After each byte is received, an

ACK bit is transmitted. Start and Stop conditions

indicate the beginning and end of transmission.

17.12.1

I2C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address or the

second half of a 10-bit address, is accomplished by

simply writing a value to the I2CTRN register. The user

should only write to I2CTRN when the module is in a

Wait state. This action will set the buffer full flag (TBF)

and allow the Baud Rate Generator to begin counting

and start the next transmission. Each bit of address/

data will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式